Iei-integration PICOe-945GSE Bedienungsanleitung Seite 88
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PICOe-945GSE Half-Size CPU Card
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The clear CMOS jumper settings are shown in 832H798HTable 5-4.
Clear CMOS Description
Short 1 - 2 Keep CMOS Setup
Default
Short 2 - 3 Clear CMOS Setup
Table 5-4: Clear CMOS Jumper Settings
The location of the clear CMOS jumper is shown in 833H799HFigure 5-6 below.
Figure 5-6: Clear CMOS Jumper
5.5.4 LVDS Panel Resolution Jumper
Jumper Label: J_LCD_TYPE1
Jumper Type:
8-pin header
Jumper Settings: See
800HTable 5-5
Jumper Location: See
801HFigure 5-7
The LVDS Panel Resolution jumper allows the resolution of the LVDS screens connected
to the LVDS1 connector to be configured. The LVDS Panel Resolution jumper settings are
shown in
802HTable 5-5.
- PICOe-945GSE 1
- Revision 2
- Copyright 3
- Manual Conventions 4
- Table of Contents 7
- List of Figures 13
- List of Tables 16
- List of BIOS Menus 18
- 1 Introduction 19
- 1.1 Overview 20
- 1.2 PICOe-945GSE Overview 21
- Page 22 22
- Page 24 24
- Serial Infrared (SIR) 25
- 2 Detailed Specifications 26
- 2.1 Dimensions 27
- 2.2 Data Flow 28
- 719HFigure 30
- 721HFigure 2-6 32
- 2.5 Intel 36
- ICH7-M Southbridge Chipset 36
- 33 MHz 38
- 724HFigure 2-11 below 40
- 2.6 LPC Bus Components 42
- 3 Unpacking 47
- 3.1 Anti-static Precautions 48
- 3.2 Unpacking 48
- 3.3 Unpacking Checklist 49
- 4 Connectors 51
- Page 52 52
- 4.1.1 PICOe-945GSE Layout 52
- Page 54 54
- 2 PS-ON 55
- 3 +5V Standby 55
- 1 HDA_SYNC 2 HDA_BITCLK 56
- 3 HDA_SDOUT 4 SB_SPKR 56
- 5 HDA_SDIN0 6 HDA_RST# 56
- 7 VCC 8 GND 56
- 9 +12V 10 GND 56
- 1 LCD Backlight Control 57
- 2 GROUND 57
- 4 GROUND 57
- 5 BACKLIGHT Enable 57
- Page 58 58
- 4.2.4 CompactFlash® Socket 58
- 747HFigure 4-7 59
- 748HTable 4-7 59
- 1 GND 2 VCC 60
- 3 Output 3 4 Output 2 60
- 5 Output 1 6 Output 0 60
- 7 Input 3 8 Input 2 60
- 9 Input 1 10 Input 0 60
- 751HFigure 4-9 61
- 752HTable 4-9 61
- 3 IR-RX 63
- 5 IR-TX 63
- 789H757HFigure 4-12 64
- 790H758HTable 4-12 64
- Page 66 66
- 793H761HFigure 4-14 67
- 794H762HTable 4-14 67
- 4.2.14 SDVO Connector 69
- 4.2.15 TV Out Connector 71
- 1 GND 2 AGREEN_Y 72
- 3 GND 4 ARED_C 72
- 5 GND 6 ABLUE_CVBS 72
- 772HFigure 4-19 74
- 2 DATA 76
- 3 DATA+ 76
- Figure 4-22: VGA Connector 77
- 5 Installation 78
- 5.1 Anti-static Precautions 79
- Read the user manual: 80
- 5.2.2 Installation Checklist 81
- 5.3 Unpacking 82
- 784HFigure 5-1) 83
- 785HFigure 5-1) 83
- 786HFigure 5-2 83
- 788HTable 5-2 85
- 789HFigure 5-4 85
- 790HTable 5-2 85
- Load Optimal Defaults 87
- 832H798HTable 5-4 88
- 833H799HFigure 5-6 below 88
- 800HTable 5-5 88
- 801HFigure 5-7 88
- 802HTable 5-5 88
- Short 2-3 +5V LVDS 90
- 5.5.6 PCIe Status Select 91
- 5.6 Chassis Installation 92
- SATA power cable 93
- Parallel port cable 93
- HDTV out cable 94
- 5.1 channel audio kit 94
- 7.1 channel audio kit 94
- [email protected] 95
- 5.7.4 SATA Drive Connection 97
- Page 98 98
- 818HFigure 5-14 99
- Page 101 101
- Page 103 103
- 858H823HFigure 5-18 104
- 862H825HFigure 106
- 6 BIOS Screens 108
- 6.1 Introduction 109
- Page 111 111
- 6.3 Advanced 112
- BIOS Menu 2: Advanced 113
- Page 115 115
- 877H840H6.3.2.1 appear 116
- Page 122 122
- DEFAULT 123
- Page 125 125
- CPU Fan PWM control 126
- Minimum Value: 0°C 126
- Maximum Value: 127°C 126
- Page 127 127
- Page 128 128
- 6.3.5 Power Configuration 128
- Page 129 129
- 6.3.5.1 ACPI configuration 129
- Page 131 131
- Page 133 133
- 6.3.7 Remote Configuration 133
- Page 135 135
- 6.4 PCI/PnP 138
- 6.5 Boot 140
- 6.6 Security 144
- 6.7 Chipset 145
- PCI/IGD DEFAULT 147
- Page 148 148
- 6.8 Exit 150
- Page 151 151
- 7 Software Drivers 152
- Page 153 153
- Page 154 154
- Page 155 155
- Page 156 156
- Page 157 157
- Page 158 158
- Page 159 159
- 7.4 VGA Driver Installation 160
- Page 161 161
- Page 162 162
- Page 163 163
- Page 164 164
- 7.5 LAN Driver Installation 165
- Page 166 166
- Page 167 167
- Page 168 168
- 7.6.1 HD Audio Installation 168
- Page 169 169
- Page 170 170
- Page 171 171
- Page 172 172
- Page 173 173
- Page 174 174
- A BIOS Menu Options 175
- B Terminology 179
- Page 180 180
- Page 181 181
- Page 182 182
- Page 183 183
- C DIO Interface 184
- C.2 DIO Connector Pinouts 185
- D Watchdog Timer 187
- E Address Mapping 190
- E.1 I/O Address Map 191
- Page 192 192
- E.2 IRQ Address Map 193
- E.3 Memory Address Map 193
- F Hazardous Materials 194
- Disclosure 194
- Page 195 195
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